1. Field of the Invention
This invention relates to a high speed semiconductor device and a method of fabricating the semiconductor device, and more particularly to a high speed CMOS (complementary metal oxide semiconductor) device having an SOI (silicon-on-insulator) structure and its method of fabrication.
2. Description of the Related Art
Extensive efforts have been made to enhance the operating speed of semiconductor devices. One way to increase the operating speed is to increase the mobility of carriers in a semiconductor material. It is well known that the mobility of a carrier depends on its crystal orientation, i.e. Miller indices of its plane. Typical values of the field effect mobility (referred to hereinafter as mobility) of two kinds of carriers in silicon of two different crystal orientations are compared below. The data are for silicon doped with an impurity, the impurity being arsenic in a p-type substrate and boron in an n-type substrate in concentrations as much as 10.sup.14 cm.sup.-3 -10.sup.15 cm.sup.-3, respectively. The mobility of the carriers in the following table is given in cm.sup.2 V.sup.-1 sec.sup.-1 :
______________________________________ Miller Indices Carrier: Electron Positive Hole ______________________________________ (100) 450 150 (110) &lt;400 190 ______________________________________
Thus, it is seen that the mobility of a positive hole in a silicon substrate having a (100) plane is only one third that of an electron. Therefore, a channel width of an FET (field effect transistor) using positive holes must be three times larger than that for electrons if the current capacity is to be kept equal to that for an FET using electrons. As integration density is always a concern, it is clear that such channel widths would not be advantageous for enhanced integration density.
Therefore, it has been proposed to employ a (100) plane for an n-channel MOSFET which uses electrons as its carrier and a (110) plane for a p-channel MOSFET which uses positive holes as its carrier. An example of one such proposal is reported in "Submicron 3D Surface Orientation Optimized CMOS Technology" by Kinugawa, et al., which was presented at the Symposium On VLSI Technology, held in San Diego, Calif., on May 28-30, 1986. The structure reported therein is schematically illustrated in FIG. 1. An n-channel MOSFET is fabricated on a (100) surface of a silicon substrate, and a p-channel MOSFET is fabricated on a surface having a (110) plane cut vertically to the (100) surface. Another proposed CMOS structure is disclosed by Kasai in Japanese unexamined patent publication Tokukai Sho 63-80561. In this structure, side planes cut vertically to the substrate surfaces are used to form transistors as well.
However, there are problems in these proposed structures. First, the fabrication processes, particularly the photolithography processes, are quite complicated due to the employment of the vertically cut surfaces. Furthermore, another problem is that in these structures a parasitic thyristor causes a latch-up phenomena between the p-type FET and the n-type FET.
In order to avoid the problems associated with vertically cut surfaces, the present inventor has proposed a partial SOI structure as shown in FIG. 2. Directly on an n-type silicon substrate 1 having a (110) plane, a p-channel MOSFET is fabricated. The p-channel MOSFET is composed of p-type source and drain regions 18 and 19, an insulating SiO.sub.2 layer 16 as a gate insulating layer, a gate electrode 17, a passivating PSG (phospho-silicate glass) layer 24 and source and drain electrodes 25a and 25b. An n-channel MOSFET of SOI structure is composed of a p-type silicon island 15 having a (100) plane, formed on an SiO.sub.2 layer 2, n-type source and drain regions 22 and 23 locally formed in the silicon island 15, an insulating SiO.sub.2 layer 20 forming a gate insulating layer, a silicon gate electrode 21, the passivating PSG layer 24, and source and drain electrodes 25c and 25d. However, an advantage of an SOI structure, that the isolation process can be carried out by only an etching process, is not enjoyed in this structure.